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RHDLURL: http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/ ODP description: RHDL (Ruby Hardware Description Language) is an HDL based on the Ruby programming language. Page title: RHDL: An Agile HDL ![]() |
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JHDLURL: http://www.jhdl.org/ ODP description: JHDL is a method of describing (programmatically, in JAVA) the components and connections in a digital logic circuit. Page title: JHDL: FPGA CAD TOOLS -- Brigham Young University ![]() |
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PerlilogURL: http://www.opencores.org/projects.cgi/web/perlilog/overview ODP description: As the name implies, Perilog uses a mix of Perl and Verilog to construct parametric hardware designs. Page title: OPENCORES.ORG Page description: OPENCORES.ORG endorses development and hosts a repository of free, open-source cores (chip designs) and supplemental platforms (boards). ![]() |
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MyHDLURL: http://www.jandecaluwe.com/Tools/MyHDL/Overview.html ODP description: MyHDL is a Python package for using Python as a hardware description and verification language. ![]() |
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Hydra Computer HDLURL: http://www.dcs.gla.ac.uk/~jtod/Hydra/ ODP description: Hydra is an HDL based on the functional programming language Haskell. Page title: Hydra Computer Hardware Description Language ![]() |
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